The present invention relates in general to electronic circuits and components therefor, and is particularly directed to a new and improved current-sensing and correction circuit with programmable, continuous compensation for temperature variations of an output switching MOSFET of a buck mode DCxe2x80x94DC converter.
Electrical power for an integrated circuit (IC) is typically supplied by one or more direct current (DC) power sources, such as a buck-mode, pulse width modulation (PWM) based, DCxe2x80x94DC converter of the type diagrammatically shown in FIG. 1. As shown therein, a controller 10 supplies a PWM signal to a (MOSFET gate) driver 20, for controlling the turn-on and turn-off of a pair of electronic power switching devices, to which a load is coupled. In the illustrated DCxe2x80x94DC converter, these power switching devices are depicted as an upper (or high side) power NMOSFET (or NFET) device 30, and a lower (or low side) power NFET device 40, having their drain-source current flow paths connected in series between a pair of power supply rails (e.g., VIN and ground (GND)).
The upper NFET device 30 is turned on and off by an upper gate switching signal UGATE being applied to its gate from driver 20, and the lower NFET device 40 is turned on and off by a lower gate switching signal LGATE from driver 20. A common node 35 between the upper and lower NFETs is coupled through an inductor 50 (which may typically comprise a transformer winding) to a load reservoir capacitor 60 coupled to a reference voltage terminal (GND). A connection 55 between inductor 50 and capacitor 60 serves as an output node from which a desired (regulated) DC output voltage Vout is applied to a LOAD 65 (shown as coupled to GND).
The output node connection 55 is also fed back to error amplifier circuitry (not shown) within the controller, the error amplifier being used to regulate the converter""s output DC voltage relative to a reference voltage supply. In addition, the common node 35 is also coupled to current-sensing circuitry 15 within controller 10, in response to which the controller adjusts the PWM signal, as necessary, to maintain the converter""s DC output within a prescribed set of parameters.
For this purpose, the controller may incorporate a current-sensing circuit of the type described in U.S. Pat. No. 6,246,220, entitled: xe2x80x9cSynchronous-Rectified DC to DC Converter with Improved Current Sensing,xe2x80x9d issued Jun. 12, 2001, by R. Isham et al, assigned to the assignee of the present application and the disclosure of which is incorporated herein. As described therein, the controller monitors the source-drain current flowing through the lower NFET 40 by way of a current-sensing or scaling resistor 37 electrically interconnected between node 35 and an current-sensing circuit 15.
The current-sensing circuit is operative to monitor the current ISENSE flowing through scaling resistor 37. This current is the product of the output current IOUT flowing from the common node 35 to the inductor 50 times the ratio of the ON-resistance RDS40ON of the lower NFET 40 to the resistance R37 of the scaling resistor 37, and is thus proportionally representative of the output current IOUT. The load current IL, namely the current I50 flowing through the inductor 50, is substantially equal to the output current IOUT minus the current ISENSE flowing through the scaling resistor 37.
As the ratio of RDS40ON to R37 is typically relatively small, the current ISENSE will be substantially smaller than the output current IOUT, so that the output current IOUT and the load current IL will have substantially similar magnitudes, making ISENSE representative of load current. The resistance of the scaling resistor 37 is selected to provide a prescribed value of current flow for the values of load current IL and/or the value of the ON-state resistance RDS40ON of the lower NFET 40. Thus, the sensitivity or magnitude of, for example, voltage droop, current limiting or trip, and current balancing incorporated into the DC/DC converter is effectively xe2x80x98scaledxe2x80x99 by selecting resistor 37 relative to the value of the on-state resistance RDS40ON of the lower NFET 40. Moreover, the voltage drop across the on-state resistance RDS40ON of the lower NFET 40 (usually negative) is accommodated in the converter without a negative voltage supply. In addition, since the ON-resistance RDS40ON of the lower NFET 40 varies with temperature, scaling resistor 37 must be selected to have a temperature coefficient which offsets the behavior of NFET 40. This may be accomplished by replacing scaling resistor 37 with a network of resistors and positive temperature coefficient thermistors.
As shown in greater detail in FIG. 2, the controller""s current-sensing circuit 15 comprises a sense amplifier 200 having a first, non-inverting (+) input 201 coupled to a controller SENSE-port 11, and a second, inverting (xe2x88x92) input 202 coupled to a controller SENSE+ port 12. The SENSE-port 11 is coupled to the grounded termination of NFET 40, while the SENSE+ port 12 is coupled through scaling resistor 37 to common node 35. The sense amplifier 200 has its output 203 coupled to the gate 213 of an NFET 210, whose drain-source path is coupled between the SENSE+ port 12 and input terminal 221 of a sample-and-hold circuit 220. Sample-and-hold circuit 220 includes PFETs 240 and 250 coupled with a capacitor 260 and input sampling switching circuitry.
In operation, the sense amplifier 200 and NFET 210 (which serves as a controlled impedance) are operative to continuously drive the controller""s SENSE+ port 11 toward ground potential. This forces the end of the current feedback resistor 37 which is connected to controller SENSE+ port 11 to be at ground potential and the end connected to common node 35 to have a negative voltage. The negative voltage at common output node 35 will be equal to the product of the output current IOUT and the on-state resistance RDS40ON between the drain and source of the lower NFET 40.
Current from the sample and hold circuit 220 flows into the drain and out of the source of NFET 210 into the SENSE+ port 11. Also flowing into the SENSE+ port 11 from the opposite direction is the current ISENSE which, as described above, is representative of load current IL. In order to maintain the SENSE+ port 11 at ground potential, sense amplifier 200 adjusts the current flowing through NFET 210 and into SENSE+ port 11 to be substantially equal to ISENSE. Since ISENSE is representative of the load current IL, the current flowing through NFET 210 and into SENSE+ port 11, as controlled by sense amplifier 200, is also representative of load current IL.
Within the controller 10, sampling control circuitry periodically supplies a sampling control signal to the sample-and-hold circuit 220, when NFET 210 is in its ON (conducting) state. In response to this sampling control signal, the sample-and-hold circuit 220 samples the current flowing through NFET 210 and stores the sampled value on capacitor 260 via node 236. Thus, the sampled current value acquired by the sample-and-hold circuit 220 is also representative of load current IL. This sampled value of sensed current is coupled from the sample and hold circuit""s output port 223 to the controller""s error amplifier circuitry that monitors the output node 55.
As pointed out above, the scaling resistor 37 that couples the common node 35 to the controller""s SENSE+ port 11 must have a temperature coefficient that offsets the behavior of the on-state resistance RDS40ON of the lower NFET 40 (which varies with temperature and may be as high as forty percent over a typical operating range). As a result, it is customary to employ some form of complicated and costly feedback network in place of resistor 37.
In accordance with the present invention, the above-discussed temperature variation problem is successfully addressed by a new and improved current-sensing and correction circuit, containing programmable temperature compensation circuitry and being configured to be incorporated into a DCxe2x80x94DC converter, such as the buck mode architecture of the type shown in FIGS. 1 and 2, described above.
The front end portion of each embodiment of the invention includes sense amplifier, NFET and sample-and-hold components described above with reference to FIG. 2. In addition to providing the sampled sense current to the sample-and-hold output terminal, an auxiliary output of the sample-and-hold circuit supplies a copy of the sampled sense current to a programming resistor having a programmable resistance. The voltage produced across the programming resistor is coupled to respective high temperature compensation (HIGHtc) and low temperature compensation (LOWtc) auxiliary sense amplifiers.
The output of the HIGHtc auxiliary sense amplifier controls a HIGHtc NFET, the drain-source path of which is coupled to a HIGHtc scaling resistor. The temperature coefficient of resistance of the HIGHtc scaling resistor is higher than that of a LOWtc scaling resistor in the source-drain path of a LOWtc NFET at the output of the LOWtc auxiliary sense amplifier. The source-drain path of the HIGHtc NFET is coupled to a current mirror, which supplies a copy of the current in the source-drain path of the HIGHtc NFET to summing node, that serves as the output of the current-sensing and correction circuit. The summing node combines the HIGHtc and LOWtc currents and the sensed current to produce a xe2x80x9ctemperature-correctedxe2x80x9d output current that is coupled to the controller""s error amplifier circuitry in place of the sensed current.
Since the temperature coefficient of the HIGHtc scaling resistor is larger than the temperature coefficient of the LOWtc scaling resistor, the ratio of the resistance of the HIGHtc resistor to that of the programming resistor will have a larger slope with temperature than the ratio of the resistance of the LOWtc resistor to that of the programmiong resistor. As a result, the contribution of the HIGHtc current flowing into the output node will decrease with increasing temperature faster than the contribution of the LOWtc current flowing out of the output node, so that the composite corrected current will decrease with increase in temperature.
For temperatures greater than a HIGHtc/LOWtc current-equality temperature, at which point the HIGHtc and LOWtc resistors are equal, the ratio of the corrected current to the sensed current will be less than 1.0; for temperatures below this current-equality temperature, the ratio of the corrected current to the sensed current will be greater than 1.0. Namely, the temperature-compensating relationship of the corrected current to the sensed current is such that the ratio of corrected current to sensed current follows a deterministic curve at temperatures other than said predetermined temperature. It should be noted that the amount of temperature compensation is set by the programming resistor.
In a second embodiment, the first embodiment is modified to substitute an additional gain stage for the current mirror that supplies the replicated HIGHtc current to the output/summing node. This provides more temperature dependence for given values of thermal coefficients of resistance.